1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a nonvolatile memory cell using a silicon nitride layer as a charge storage layer, a fabrication method for the same and semiconductor integrated circuit systems.
2. Description of the Related Art
As one of nonvolatile semiconductor memory devices which enable electrically writing and erasing, a MONOS memory cell using a silicon nitride layer for a charge storage layer has been known.
A gate insulating layer of the MONOS memory cell is specifically formed in a stacked structure of a tunneling insulating layer, a silicon nitride layer and a block insulating layer.
Different from a floating gate memory cell structure, a gate electrode of the MONOS type cell has a single layer structure. Thus, if the MOMOS memory cell array is formed together with a typical MOS transistor having a single gate layer structure similar to that of the MONOS memory cell on the same substrate, it is characterized that commonality of a process thereof can be easily realized.
As a technology for achieving a higher speed of the MOS transistor, a salicide structure and a process for siliciding surfaces of a gate electrode and source and drain diffused layers have been presented. In this silicide structure, since a silicon substrate of the source and drain diffused layer regions reacts with a metal to be silicided, there is a problem of junction leakage which occurs when the source and drain diffused layers are shallow.
Therefore, if the MONOS memory cell and a logic circuit are fabricated on a same chip in hybridization, application of the salicide structure makes the problem serious. It is because the source and drain diffused layers of the MONOS type memory cell are shallow compared with those of the typical MOS transistor and, if these layers are simultaneously silicided, junction leakage of the source and drain diffused layers easily occur in the memory cell array region.